Transactional Memory
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چکیده
Shared memory parallel architectures present a single unified address space to each processor. Usually the memory is physically distributed across the system but each processor is able to access any part of it through a single address space. The system hardware is responsible for presenting this abstraction to each processor. Communication between processors is done implicitly through normal memory load and store operations. For this reason, shared memory architectures generally have much lower processor-to-processor latencies than message passing architectures which often rely on software to handle communication. In addition, the shared memory programming environment is more natural than that of message passing and is better suited for many applications. Often the ability to perform several memory operations atomically is required for correct program execution. Unlike message passing systems, achieving such atomicity in shared memory is a nontrivial task. Traditionally, a technique called locking has been used to solve this problem. A lock is a memory location that, by convention, protects a block of code that needs to be run atomically. Once a processor obtains the lock, that processor can execute the atomic block. All other processors wanting to execute that code must wait until the lock is released. The processor holding the lock must release it once it is done executing the atomic block. This entire mechanism is a convention that is maintained by software alone. The hardware only provides the necessary mechanisms to obtain, release, and check the status of any lock.
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تاریخ انتشار 2003